IJSRD - International Journal for Scientific Research & Development| Vol. 5, Issue 1, 2017 | ISSN (online): 2321-0613

The power consumption and delay optimization has been the main concerns for the VLSI technology. In this project we propose a new adiabatic technique using diode connected transistors. This technique emphasizes on reduction of power by lowering the non-recoverable power consumption in adiabatic circuits. This technique achieves full adiabatic operation by providing separate charging and discharging paths. The PMOS devices provide the charging path while the diode connected NMOS devices provide low resistance discharge path which helps in reduction of power dissipation in the circuit. This project compares the different logic style 2:1 multiplexers like CPL, EEPL and PFAL with the proposed design (ADDL) in terms of power and delay. The power consumption and delay is reduced up to a sufficient level with the help of new adiabatic logic technique. Nibble multiplexer is also designed using proposed logic. All the simulations have been performed by using TSpice.